The memory cells of dynamic random access memories (DRAMs) are comprised of two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) cells which provides a substantial increase in component density.
However, the extension of dynamic random access memories beyond the megabit range has placed large demands on the storage capacitance in single transistor memory cells. The problem is compounded by the trend for reduction in power supply voltages which results in stored charge reduction and leads to degradation of immunity to alpha particle induced soft errors, both of which require that the storage capacitance be even larger. As the cell size for dynamic random access memory (DRAM) cells is reduced to that necessary for Gigabit density and greater, there are three major impediments to cell size reduction which can be overcome only by significant innovation in the cell structure.
Cell structures used through the 256 Megabit generation have been fundamentally limited to a size of at least 8 F.sup.2, where F is a minimum lithographic feature size. This size limitation is imposed by the wiring requirements of passing both an active and passing word lines through the cell to achieve the low noise benefits of folded bit line architecture. This limitation can be removed by either relinquishing the folded bit line architecture or by devising a sub lithographic wiring technique. A further limitation is imposed by the area required to form the source region, the drain region and the channel region of the FET array device on a planar surface. Another limitation is imposed by the area that is required for fabricating the storage capacitor which, in a stacked capacitor technology, must compete with the bit line and word line wiring for space above the silicon surface.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory cell structure for a semiconductor memory device, such as dynamic random access memory device, which employs a folded bit line architecture and in which the surface area of the memory cells is minimized, providing a memory cell structure that is less than 8 F.sup.2 in size, resulting in increased density for the memory device.